FPGA implementation of image encryption and decryption using AES 128-bit core
M. Pradeep K. Priyanka, E. Lakshmi Prasad, A.R. Reddy · 2016
AES is one of the standard algorithm and widely used to encrypt and decrypt the data. In this paper, image encryption and decryption algorithm implemented by using AES 128-bit core. Here, image information is converted into a hexadecimal format using Matlab code and this plain hexadecimal data are transmitted to the FPGA via UART for encryption. Thus, the same process is also used for Decryption. The entire AES 128-bit core is simulated and synthesized for Spartan-3E-1600E FPGA using Xilinx ISE 14.3. Therefore, the experimental results are measured and compared with respect to area, power, and latency. The total amount of area occupied for encryption is 6% of slices, 2% of slice Flip flops, 5% of 4-input LUTS and 44% of BRAMS, latency for 128-bit is 6.645 ns and the amount of power consumption is 441.91 mW. Similarly, for the decryption amount of area occupied is 7% of slices, 2% of slice Flip flops, 7 % of 4-input LUTS and 55% of BRAMS, latency for 128-bit is 7.770 ns and the total amount of power consumption is 442 mW.