Design of High Speed Floating Point Multiplier Unit
C. M. Kalaiselvi, D. Maheswari, Prabhat Nagarajan · Computer Science and Software Engineering · 2015
In computing, floating point describes a method of representing an approximation of a real number in a way that can support a wide range of values. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. Architecture for a fast floating point multiplier yielding with the single precision IEEE 754-2008 standard has been used in this project. The floating point representation can preserve the resolution and accuracy compared to fixed point. Pipeline is a technique where multiple instructions are overlapped in execution. Multiple operations performed at the same time by pipeline will increase the instruction throughput. The multiplier implementation in floating point multiplication is done by Modified Booth Encoding (MBE) multiplier to reduce the partial products by half. Radix-8 Booth Encoder circuit generates n/3 the partial products in parallel.