Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test
Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue · IEICE Technical Report; IEICE Tech. Rep. · 2013
FPGAs are attractive devices due to their low development cost and short time-to-market, and widely used not only for reconfigurable purpose but also as applicationdependent embedded devices for low-volume products. This paper presents a scan-based BIST architecture for testing of application-dependent circuits configured on FPGA. In order to build up BIST components such as LFSR, MISR and scan chains for test points, the proposed architecture efficiently utilizes memory blocks, instead of logic elements, which are unused for application-dependent circuits. The proposed BIST architecture provides enhanced scan functionality for test points and performs a hybrid test application of LOC and enhanced scan to improve delay test quality. Experimental results show that the proposed BIST architecture achieves high delay test quality with efficient resource utilization. keywords: FPGA, BIST, delay test, DFT.