FPGA design of the fast decoder for burst errors correction
Evgeniy A. Mytsko, Andrey N. Malchukov, Иван Владимирович Зоев, Светлана Евгеньевна Рыжова, V. L. Kim · Journal of Physics Conference Series · 2017
The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check_pattern, decoder2 , implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ∼20 ns.