An Efficient Scenario Based Testing Methodology Using UVM
Khaled Fathy, Khaled Salah · 2016
Most of modern verification architects use randomness supported by system verilog (SV) to enable defining a generic path for a test to follow. This generic path stresses on a subset of features, and allows randomization to explore corners in depth. Setting up such test case requires a well-defined stimulus generation methodology that consumes less time to cover all the corner-cases. Moreover, Off-the-shelf scenario libraries, synchronization and scheduling process methodology for the parallel stimuli need to be reused across several test cases. In this paper, a novel methodology for creating test scenarios is proposed. Moreover, making use of object oriented principles to build composite layered scenario sequences with a generic parallel stimuli synchronization process is introduced. The proposed methodology is built as a generic library code to be reused in many designs. The results of applying this methodology on test cases show enhancements on reusability, test cases count, coverage closure and performance.