Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems
Xin-Yu Shih, Hong-Ru Chou · 2017
This work proposes a reconfigurable low-area-cost computing kernel engine for 1-stage-of-radix-5, 2-stage-of-radix-3, and 4-stage-of-radix-2 SDF FFT applications. By using TSMC 90nm CMOS technology, our design with higher hardware utilization ratio has a synthesis area occupation of 0.093mm2, only increasing 10.7% circuit overhead with respect to pure radix-5 computing kernel design.