Architectural performance analysis of FPGA synthesized LEON processors
Corentin Damman, Gregory Edison, Fabrice Guet, Éric Noulard, Luca Santinelli, Jérôme Hugues · 2016
Current processors have gone through multiple internal optimization to speed-up the average execution time e.g. pipelines, branch prediction. Besides, internal communication mechanisms and shared resources like caches or buses have a significant impact on Worst-Case Execution Times (WCETs). Having an accurate estimate of a WCET is now a challenge. Probabilistic approaches provide a viable alternative to single WCET estimation. They consider WCET as a probabilistic distribution associated to uncertainty or risk.