BIT STREAM MODIFICATION TO IMPROVE THE DEBUGGING CAPABILITIES OF RE CONFIGURABLE COMPUTING SYSTEMS
Faisal Muslehuddin · OhioLink ETD Center (Ohio Library and Information Network) · 2002
With the increasing design complexity of applications implemented on Field Programmable Gate Array (FPGA) based hardware platforms the time for debugging becomes a major bottleneck in achieving early time to market goals.Traditionally designs implemented on SRAM based FPGAs have been debugged in a manner similar to ASIC designs using simulation during the early stages of the design process.However, FPGA device features such as configuration readback, reprogramability, and clock stepping support the debugging of designs directly on the FPGA-based target platform thus speeding up the debugging and verification process.Recently FPGA vendors and academic researchers have introduced integrated logic analyzer (ILA) cores that are added to a user's design in support of such in-situ debugging.In this thesis we have developed a method to enable addition of such cores at the last step of the FPGA design flow.This can ease and expedite the process of debugging designs implemented on FPGA based systems by improving their execution control, reducing the time taken to modify the debugging functionality and hence aid in achieving early time to market goals.The process of developing these debugging techniques was divided into two phases.