A METHODOLOGY FOR INTERCONNECT TESTING OF NETWORK-ON-CHIP
Kishore R Maddi · OhioLink ETD Center (Ohio Library and Information Network) · 2005
Generally, the performance of a digital system today is limited by its communication or interconnection, not by its logic or memory.In a high-end system today, most of the clock cycles are spent on wire delay, not gate delay.For a deep sub-micron technology system-on-chip (SoC) consisting of hundreds of cores, communication is one of the bottle-necks to meet performance requirements.Network-on-chip (NoC) is one of the communication architectures for future SoC's.NoC is reusable, scalable and supports parallel communication at the expense of more design complexity.Testability of NoC guarantees the proper operation of the communication architecture.Incorporating testability at the design level enables to implement better test strategies to reduce test time.Interconnect is one of the major components of the NoC architecture.In this thesis, we adapt a distributed routing methodology to the NoC.The methodology reduces the design complexity, improves the performance of the NoC, and also enables to incorporate interconnect testing with minimum design overhead by using the extra address space.A priority-based approach is developed to derive the minimum number of con gurations for testing interconnects for the 2D mesh NoC.This approach reduces the redundancy in testing interconnects, and thus test cost.Further, theoretical analysis demonstrate that only two test con gurations are required to test all interconnects of any (m x n) 2D mesh NoC with zero redundancy.I am always excited about the acknowledgements because it is an opportunity for me to thank the special people who are responsible for my success.I would always remain indebted to these people.I would like to thank my thesis advisor Dr. Wen-Ben Jone for his guidance and support.He had taught me valuable lessons for life and I have always enjoyed my interactions with him.I can never forget his valuable suggestions in the successful completion of my Master's program.I would like to