A novel implementation of 32 bit extended ALU Architecture at 28nm FPGA
Nidhi Gaur, Anu Mehra, Deepika Kamboj, Devyani Tyagi · 2016
This paper proposes a new approach for 32 bit Arithmetic and Logic Unit for multifunctional processors. The proposed ALU has a novel instruction set including Parity checker, Parity Generator, Binary to Gray converter, gray to binary converter and Manchester encoder decoder along with conventional ALU operations. This extended ALU caters the need of cryptographic processors where an extended security could be provided using novel operation sets. Present ALU Architecture is simulated in Xilinx Vivado 14.4 tool and implemented on 28nm zynq 7000 FPGA board. Total on chip power used in presented ALU is 0.123 W only.