DESIGN AND TEST OF HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURE FOR HIGHLY INTEGRATED SYSTEMS
Ming Li · OhioLink ETD Center (Ohio Library and Information Network) · 2006
A layered architecture called Network-on-Chip (NoC) has been recently proposed for global communication in a complex System-on-Chip (SoC) design to meet the performance requirements, and many new design and testing issues come up correspondingly.In this work, we aim to develop an efficient test strategy for NoC embedded core testing with a high performance router architecture which can support normal mode as well as testing mode operations.For normal mode router design, we propose to use a novel dynamic XY (namely DyXY) routing method, which provides adaptive routing based on congestion conditions in the proximity, and ensures deadlock-free and livelock-free features at the same time.Analytical models based on queuing theory are developed for DyXY routing in two-dimensional mesh architectures, and analytical results match very much with the simulation results.It is observed that DyXY routing can achieve much better performance when compared with static XY routing and odd-even routing.Hardware is also designed to support the proposed DyXY routing method efficiently.For the embedded core testing, we propose a multiple-data-flit-format (MDFF) test data transportation concept, a heuristic wrapper scan chain configuration method, and a test scheduling algorithm which considers both channel capacity and data flit interleaving in the channels and routers.By applying