A Proposal for a Standard Synthesizable Subset for SystemVerilog-2005: What the IEEE Failed to Define
Stuart Sutherland · 2006
SystemVerilog adds hundreds of extensions to the Verilog language. Some of these extensions are intended to represent hardware behavior, and are synthesizable. Other extensions are intended for testbench programming or abstract system level modeling, and are not synthesizable. The IEEE 1800-2005 SystemVerilog standard(1) defines the syntax and simulation semantics of these extensions, but does not define which constructs are synthesizable, or the synthesis rules and semantics. This paper proposes a standard synthesis subset for SystemVerilog. The paper reflects discussions with several EDA companies, in order to accurately define a common synthesis subset that is portable across today's commercial synthesis compilers.