Low‐latency digit‐serial dual basis multiplier for lightweight cryptosystems
Che Wun Chiou, Chiou‐Yng Lee, Jim‐Min Lin, Yun‐Chi Yeh, Jeng‐Shyang Pan · IET Information Security · 2017
Various cryptosystems, such as elliptic curve and pairing‐based cryptosystems, in resource‐constrained security applications rely on finite field multiplication. For applications such as these, a digit‐serial multiplier has the potential features to achieve a trade‐off between space and time complexities. The authors propose an efficient decomposition of the multiplication into four independent sub‐multiplication units to facilitate parallel processing, which is additionally facilitated by the systolic structures of the sub‐multiplication units. The proposed architecture uses a four‐bit scheme to construct a novel processing element, instead of using only one bit as is currently used in similar multipliers. The results of the synthesis show that the proposed digit‐serial dual basis multiplier eliminates up to 96% of the critical path delay.