Development of Advanced Encryption Standard Architecture with Sbox Parity
M. Vanitha, Srinivasan Subha · Walailak Journal of Science and Technology (WJST) · 2016
In this paper, an efficient AES (Advanced Encryption Standard) has been designed so that security levels can be increased which is caused due to faults and errors. The AES algorithm includes mainly 4 transformations, which are Sub-byte, Shift row, Mix column, Add round key. The security of Sbox has been increased by using even parity, which is used to detect faults rather than correction. A FIFO (First-In First-Out) is also considered to store the parity bits of Sbox. The expected parity bit of the output is predicted initially with the help of look up table (LUT) and compared with output parity bit. By this we can improve the fault coverage of Sbox. Since the Sbox parity architecture involves more MUX and XOR, their area is reduced by using the Binary Decision Diagram (BDD) approach and a pass transistor implementation of MUX which reduces the area drastically. Verilog HDL language is used to model the architecture and verification was done on Modelsim. Design, synthesized using a Cadence Register Transfer Level (RTL) complier tool. The synthesized result shows that there is an area overhead of 8 % and high fault coverage of 99.23 %.