User-friendly design approach for analog layout design
Yongfu Li, Zhao Chuan Lee, Vikas Tripathi, Valerio Pérez, Yoong Seang Jonathan Ong, Chiu Wing Colin Hui · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2017
Analog circuits are sensitives to the changes in the layout environment conditions, manufacturing processes, and variations. This paper presents analog verification flow with five types of analogfocused layout constraint checks to assist engineers in identifying any potential device mismatch and layout drawing mistakes. Compared to several solutions, our approach only requires layout design, which is sufficient to recognize all the matched devices. Our approach simplifies the data preparation and allows seamless integration into the layout environment with minimum disruption to the custom layout flow. Our user-friendly analog verification flow provides the engineer with more confident with their layouts quality.