A 65nm ASIC based 256 NIST prime field ECC processor
Hamad Marzouqi, Mahmoud Al‐Qutayri, Khaled Salah, Hani H. Saleh · 2016
This paper presents a 65 nm ASIC based 256 NIST prime field ECC processor. To achieve high throughput, extensive pipelining techniques were applied to realize the Karatsuba-Ofman Multiplier along with enhanced NIST Reduction Formula. The processor architecture was implemented using Global Foundry 65 nm Low Power (LPE) technology. The processor runs at a maximum frequency of 244 MHz and performs single scalar point multiplication within 1.48 ms. The processor occupies 0.472 mm2die area with 114 k gates and consumes a maximum power of 6.8 mW. Further to ASIC implementation, the processor was prototyped using a FPGA Virtex 5 device exhibited a throughput improvement of 140% over previously published results. Both ASIC and FPGA implementations showed competitive results when compared with state of the art ECC processors found in the literature.