FPGA implementation of an efficient router architecture based on DMC
Geethu Jayan, P. P. Pavitha · 2016
System on Chip enables us to integrate maximum amount of technology in less space. For establishing effective communication among the SoCs, traditional bus architecture has been used. But this becomes insufficient when the data traffic has increased. Network on Chip (NoC) is a solution for this issue. In NoC, the traditional bus structure is replaced with a network which consists of routers, links and IPs. Data packets are transmitted over this network. A modified NoC router architecture is proposed in this work, in which the virtues of Decimal Matrix Code (DMC) are utilized. In the earlier works, Hamming code served the purpose of error detection, but it was limited to a single bit. With the integration of DMC, errors up to five bits can be detected and corrected at the same. This architecture is applicable for two dimensional NoCs like Dynamic Network on Chip (DyNoC). The loopback module, which is a distinct feature of DyNoc, helps to dynamically re-route the data packets, if the neighbouring routers become unavailable all of a sudden. The routing operation is governed by the XY routing algorithm. The analysis of the proposed router architecture in terms of the error detection and correction capability is carried out in this work. The architecture is modelled using VHDL in Xilinx ISE Design Suite 13.2 and implemented in SPARTAN 3 FPGA.