FPGA implementation of LBlock lightweight block cipher
Md. Nazmul Hasan, Md. Tariq Hasan, Rafia Nishat Toma, Md. Maniruzzaman · 2016
The ubiquitous computing era is characterized by wide deployment of resource constraint devices. Secure communication between such devices encounters a big challenge due to their resource limitation. The lightweight cryptographic algorithms are developed to address this challenge. In this work, implementation of LBlock, a lightweight encryption algorithm is investigated in Altera DE1 FPGA board. The encryption algorithm involves a Feistal structure and requires 32 clock cycles to encrypt 64-bit data. The implementation results show that it requires 326 Logic Elements (LEs) in Cyclone II EP2C20F484C7 platform. The maximum clock frequency was reported as 156.32 MHz and a corresponding power consumption of 107.62 mW. Also, the throughput is found as 312 Mbps. These results are better as compared to some other lightweight encryption such as XTEA and Hummingbird for the same FPGA platform.