Embedded implementation of efficient accelerator architecture
Linu M Jiji, Ragimol · 2016
Hardware acceleration has been proved as an extremely promising implementation strategy for the digital signal processing (DSP) and multimedia application domain. An accelerator module can be attached to digital signal processors for enhancing the performance. It enhances the performance or functionality by executing certain function in the accelerator instead of executing in the processor core. Adding accelerators is suitable in cases where the flexibility is essential and in most of the DSP applications. The accelerator module mainly consists of flexible computational units (FCUs). The structure of the computational unit is designed to enable high performance flexible operation based on a set of operation templates found in DSP kernels. One of the main advantages of this multiplier is that the recoding scheme used in it reduces the number of partial products which in turn reduces the area and the delay. A high performance architectural scheme is designed by combining both the architectural and arithmetic levels of optimization. As a result of architecture level of optimization area can be reduced. Conventional adders are replaced with fast adders to reduce the propagation delay. The proposed solution forms an efficient design tradeoff point delivering optimized latency/area. It also provides high computing performance, real time processing to variety of applications ranging from sensors to servers.