11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology
Ryuji Yamashita, Sagar Magia, Tsutomu Higuchi, Kazuhide Yoneya, Toshio Yamamura, Hiroyuki Mizukoshi, Shingo Zaitsu, Minoru Yamashita, Toyama Shunichi, Norihiro Kamae, Juan Lee, Shuo Chen, Tao Jiawei, William Mak, Xiaohua Zhang, Ying Yu, Yuko Utsunomiya, Yosuke Kato, Manabu Sakai, Masahide Matsumoto · 2017
High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash, recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density by increasing the number of stacked layers. The first 3b/cell 3D-flash used 32 layers in 2015, and reached 48 layers in 2016. Also, density as high as 2.62 and 4.29Gb/mm2were achieved, as shown in Fig. 11.1.7. This rapid scaling of 3D-flash technologies is possible since it is free from the lithography limitation mentioned above. This paper describes a 512Gbit 3b/cell flash fabricated with a 64-word-line-layer BiCS technology. In this work, we implemented three technologies: four-block even-odd-combined row decoding to effectively address the increase of stacked layers; unselected string pre-charge operation to improve endurance and reliability, and; shielded BL current sensing to enhance read throughput. Figure 11.1.1 shows the die photo and the summary of key features.