Generation of High Coverage Property Set Using Counterexamples
Takeshi Matsumoto, Yeonbok Lee, Yoshida Hiroaki, Yomiya Hisashi, Masahiro Fujita · IEICE Technical Report; IEICE Tech. Rep. · 2008
When we design a large system including hardware and software, verification in specification-level is very important to avoid design bugs from the subsequent design-levels such as system-level and behavior-level. However, partly because the specification documents itself has unclarity and ambiguity, correctly writing properties to be kept in designs is difficult. In this work, we propose a high-level design flow considering verification and property derivation in that flow. In general, the quality of property checking is decided by the completeness of a set of given properties. Therefore, metrics to measure the completeness of the property set and methods to generate properties with high completeness are required. We propose a transition-based coverage metric that is defined in finite state machine of the system specification. Through a case study of an elevator controller design, we also show a way to generate properties that can improve the coverage from counterexamples found in simulation.