Optically reconfigurable gate array platform for mono-instruction set computer architecture
Hiroki Shimba, Minoru Watanabe · 2017
The operating clock frequency of the latest processor has never been increased because of recent process issues. A game change must occur to achieve progress in clock frequencies. Therefore, we propose a mono-instruction set computer (MISC) architecture based on optically reconfigurable gate array architecture. The MISC architecture consists of various single instruction processor cores having only one instruction. Using the MISC architecture, the processor performance can be increased drastically. However, the only requirement is the use of a high-speed dynamically reconfigurable device or an optically reconfigurable gate array (ORGA). As described herein, we present the latest ORGA and discuss benefits of MISC architecture based on the ORGA.