8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator
Monodeep Kar, Arvind Singh, Sanu K. Mathew, Anand Prem Rajan, Vivek K. De, Saibal Mukhopadhyay · 2017
Power side-channel attacks (PSCA), e.g. Differential Power Analysis (DPA) and Correlation Power Analysis (CPA), are major threats to the security of crypto engines in SoC platforms. Circuit-level SCA countermeasures to achieve data-independent supply current patterns via implementation of crypto engines using non-conventional logic (complemented or charge recovery) and local switched-capacitor-based supply current equalization have been demonstrated. The feasibility of using bandwidth-limited integrated low dropout regulators, multi-phase switched-capacitor VRs with phase-randomization and integrated inductive voltage regulators (IVR) to enhance PSCA resistance have been explored before via simulation studies. In this paper, we demonstrate improved PSCA resistance offered by an on-die all-digital high-frequency IVR in 130nm CMOS for a standard (unprotected) 128b Advanced Encryption Standard (AES) core designed in static CMOS logic. The IVR features a configurable digital proportional-integral-derivative (PID) controller, a digital discontinuous conduction mode (DCM) controller, and a loop randomization (LR) block, all of which are utilized to enhance PSCA resistance with minimal power/performance/area overheads, while maintaining adequate local voltage regulation and transient performance.