3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration
David Greenhill, Ron Ho, David M. Lewis, Herman H. Schmit, Kok Hong Chan, Tong Andy, Sean Atsatt, Dana L. How, McElheny Peter, Duwel Keith, Schulz Jeffrey, Faulkner Darren, G. Iyer, George Chen, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Ty Garibay · 2017
A Field Programmable Gate Array (FPGA) family was designed to match a programmable fabric die built in 14nm process technology with 28Gb/s transceiver dice. The 2.5D packaging (Fig. 3.3.1) uses embedded interconnect bridges (EMIB) [1]. 20nm transceivers were reused enabling a transceiver roadmap independent of FPGA fabric. Fig. 3.3.2 shows a 560mm2fabric die and six transceiver dice. The programmable fabric contains 2.8M logic elements, DSP, memory components, and routing interconnect operating at up to 1GHz. Applications drove the need for improved flexibility and security of the FPGA configuration system. A triple-modular redundant microprocessor-based secure device manager (SDM) was designed and is programmed by embedded software.