Application of LFSRs for Parallel Sequence Generation in Cryptologic Algorithms.
Sourav Mukhopadhyay, Palash Sarkar · 2006
We consider the problem of e#ciently generating sequences in hardware for use in certain cryptographic algorithms. The conventional method of doing this is to use a counter. We show that sequences generated by linear feedback shift registers (LFSRs) can be tailored to suit the appropriate algorithms. For hardware implementation, this reduces both time and chip area. As a result, we are able to suggest improvements to the design of DES Cracker built by the Electronic Frontier Foundation in 1998; provide an e#cient strategy for generating start points in time-memory trade/o# attacks; and present an improved parallel hardware implementation of a variant of the counter mode of operation of a block cipher.