A Temperature-Aware Power Estimation Methodology
Madhu Saravana, Sibi Govindan, Stephen W. Keckler, Sani Nassif, Erdem Acar · 2008
Abstract Reducing power consumption, improving designer productivity and mitigating thermal effects are grandchallenges for future CMOS-based designs in the nanometer regime [1]. Solving these challenges requires a power estimation methodology that is temperature aware and simple, fast and accurate. In this paper, wepresent such a power estimation methodology that utilizes data from different levels of modeling abstraction and is applicable to both current and future processors. Our methodology leverages design data from the gate-level model and activity factors from the structural RTL model and refines the initial power estimates based on a thermal and power grid model. We demonstrate our methodology using a SOC-style, tiled, general purpose,chip multiprocessor implemented at 130nm and provide scaled-down estimates at 90nm, 65nm, 45nm and 32nm technologies. 1