A Novel Micro-Architecture Using a Simplified Logistic Map for Embedded Security
P. Harsha · IEEE Embedded Systems Letters · 2017
A novel scheme for the introduction of chaos-based security into embedded systems at an architectural (hardware) level is presented in this letter. The logistic map is simplified for use in resource-constrained microcontrollers in the encryption of digital data through interface protocols like SPI etc. This letter, as an example, presents an outline of the registers and their associated logic for such an 8-bit chaotic modulator. Correlation analyses along with a Gottwald-Melbourne test proved its robustness for security. This letter develops a micro-architecture that involves the proposed chaos generator and discusses the control methods by which data is to be handled for seamless encryption/decryption without processor involvement. The descriptive work presented is proposed to be a silicon level encryption technique and its implications are generalized to be used with other word sizes and interface protocols, in any microcontroller.