Automated generation of dynamic binary translators for instruction set simulation
Katsumi Okuda, Minoru Yoshida, Haruhiko Takeyama, Minoru Nakamura · 2017
Instruction set simulators (ISSs) are indispensable tools for developing new architectures and embedded software. Due to the increasing variety of architectures and time-to-market pressure, it is important to efficiently develop fast ISSs based on dynamic binary translation. However, the implementation of such ISSs needs more effort than interpretive ISSs. In this paper, we propose a novel framework that generates ISSs based on dynamic binary translation from descriptions of interpretive ISSs. Our results on SH, MIPS64, and ARM show that the generated ISSs are 1.4 to 13.4 times faster than their original interpretive ISSs.