Novel Hardware-Software Architecture for the Recursive Merge Filtering Algorithm
Piyush S. Jamkhandi, Amar Mukherjee, Kunal Mukherjee, Robert W. Franceschini · 2000
As reconfigurable devices move to the forefront of mainstream processing, the spectrum of application areas for such devices is also increasing. One such area is image processing. In this paper we present a novel hardware-software codesign architecture for the computation of the Discrete Wavelet Transform (DWT), based on a new Recursive Merge Filtering (RMF) algorithm. The architecture aims at reducing the overall data routing during the computation of the DWT. The method shows how data routing can be transformed into a series of index computations carried out on the reconfigurable device. The architecture applies hardware/software codesign principles for task division among the available processing resources and uses memory resources closer to the FPGA to avoid the main memory accesses and this reduces the processing time and access time. The paper also proposes ideas based on memory bank to further enhance the performance of the proposed architecture. The architecture is based on a dynamically reconfigurable device, the Xilinx XC6200 on the H.O.T Works Board used to carry out the data routing by a series of index computations. The complex computations are restricted to the main processor and the simple addition/subtraction tasks for data routing are based on the FPGA.