100-Mb/s enhanced data rate MIL-STD-1553B controller in 65-nm CMOS technology
Prateek Pendyala, Vijaya Sankara Rao Pasupureddi · IEEE Transactions on Aerospace and Electronic Systems · 2016
As the demand for higher communication bandwidth in avionics increases, the need for a faster and error-free high speed 1553 bus network has become essential. Instead of installing new bus wiring, it would be useful if these buses are driven at higher data rates by retrofitting redesigned 1553 controllers. This work proposes a 100-Mb/s enhanced data rate MIL-STD-1553B controller chip in 65-nm, 1.2 V CMOS technology. The controller features an integrated remote terminal (RT), bus monitor (BM), and bus controller (BC), thus offering a complete 1553 solution at this increased throughput. Firstly, the controller incorporates a synchronous back-end and host processor interface to a true dual port memory to enable faster memory accesses. Secondly, the controller employs majority-based free-running sampling decoders, suitable to interface with 100-Mb/s analog transceivers. Finally, the enhanced 1553 control unit uses scaled-up state machines to manage the scheduling, storage, and retrieval of 1553 messages, to facilitate faster message transfer over the 1553 buses. Also, the proposed enhanced data rate controller's implementation and code testing is performed on a Spartan-6 FPGA Chipscope platform to prove its functionality for the target throughput. This prototype controller chip delivers 100 Mb/s over MIL-STD-1553B buses while consuming 29.86 mW at 100% transmitter duty cycle and occupying an area of 115470 μm2for a target bit error rate (BER) of 10-7.