A FPGA-based LVL-2 Supervisor using Enable++
Hubert Högl, Andreas Kugel, J. Ludvig, Reinhard Männer, Klaus-Henning Noffz, Stephan Rühl, R. Zoz · 1996
One of the most performance critical components of the ATLAS LVL-2 trigger is the central control instance of the system: the supervisor. Its primary task is the distribution of Regions-of-Interest (RoI) and the resource management of the LVL-2 processor farm. In this paper we propose to program the supervisor into the FPGA processor Enable ++ . The implementation in a single processing unit of Enable ++ is able to manage a LVL-2 farm of 400 processors, for larger farms the number of processing units can be increased. The current implementation runs with a clock frequency of 17.9 MHz resulting in a overall latency of 20 ¯s. A major advantage is that it avoids the development of dedicated hardware accelerators. 1 Introduction All farm-based solutions for the ATLAS LVL-2 and LVL-3 trigger need a central instance of control: the supervisor. Its main tasks are the allocation of processors (resources), the distribution of Region-of-Interests (RoI), and the detection of and recovery from e...