Dual Processing Engine Architecture to Speed Up Optimal Ate Pairing on FPGA Platform
Zhongyuan Hao, Wei Guo, Jizeng Wei, Da‐Zhi Sun · 2016
Recently, pairing based cryptography has drawn a lot of attention since it is the key technology to construct identity based encryption schemes. Major operations of pairing are elliptic curve computations defined upon finite field arithmetic. Hardware implementation of large prime field operation is critical to improve the practicality of pairing based cryptography. In this paper, we present a parallel processing architecture of cryptoprocessor for optimal ate pairings over BN-curves in prime field. The proposed design contains two arithmetic processing engines to complete prime field operations in parallel. Each engine is designed by the unified Fp arithmetic unit to save hardware resources. This architecture can also be used to implement RSA and ECC cryptography schemes in parallel to satisfy industry demand. The design is implemented on a Virtex-5 FPGA device. The result shows our design consumes 10592 Slices and computes optimal-ate pairing within 283,111 clock cycles, achieving a better balance between speed and area than other designs.