Implementation of high speed Vedic BCD Multiplier using Vinculum method
G. Sree Lakshmi, Kaleem Fatima, B. K. Madhavi · 2016
This paper presents a BCD Multiplier that operates on Vedic Mathematics called Vedic sutras. It uses a method called Vinculum which converts higher complex numbers into its simplest form. In Decimal number system the numerials 6,7,8,9 are called high complex numbers and numbers consisting of 6,7,8,9 are converted into 4,3,2,1 there by total number or any number is between 1 to 5 digits only for any arithmetic operation. This feature reduces Carry generations and Carry propagations there by performance parameter like delay reduces especially in adders and multiplier structures. We choosen an arithmetic operation multiplication and it is compared with Conventional Multiplier [1] [2] [3] and Vedic Multiplier[5] and it has been observed that improvement in speed is 83.5% in case of conventional multiplier and 47.8% in case of vedic multiplier which is suitable for High Speed Applications. The Architecture is implemented using Xilinx Vertex 4 FPGA and the same is done using Cadence Digital Encounter Tools of TSMC180nm Technology. The results indicate that the proposed BCD multipliers is very efficient in terms of speed when compared to decimal multipliers implemented with direct manipulation of BCD numbers.