Implementation of Pipelined Radix-2 FFT using SDC and SDF architecture
Deepika Hiremath, B Rajeshwari · 2016
Implementation of the Pipelined Radix_2 FFT using Single path Delay Commutator and Single path Delay Feedback (SDC & SDF) architecture is presented. This architecture includes 3 stages of the SDC and 1 stage of SDF. This approach makes use of less hardware resources and also shares the same resources as it is pipelined architecture. Thus reducing the number of complex multipliers and the adders used in the architecture as compared with other Radix_2 SDC and SDF architecture when used alone.