Evaluation of an HEVC hardware IME module using a SoC platform
Estefanía Alcocer, Otoniel López-Granado, Manuel Perez Malumbres, R. Gutiérrez · 2016
In the HEVC standard, motion estimation is one of the most complex task of the video encoder, requiring a great percentage of the encoding time mainly due to (a) a large set of Coding Tree Unit partitioning modes, (b) the presence of multiple reference frames, and (c) the varying size of Coding Units in comparison with its predecessor H264/AVC. In addition, HEVC adopts Variable Block Size Motion Estimation to obtain advanced coding efficiency. In this work, we evaluate a hardware IME design when applied to an System-On-Chip platform. In this evaluation we will measure the impact on the Rate/Distortion performance when applying different CTU sizes and reference search areas. Furthermore, we will evaluate the effect of the DMA transfers required in the computational performance. This architecture has been synthesized and implemented on the Xilinx SoC, Zynq-7 Mini-ITX Motherboard XC7Z100 (xc7z100ffg900-2). We have evaluated our hardware IME design using different CTU size configurations, search area sizes and DMA burst sizes in order to determine the maximum speed gain respect to the HEVC reference software. Results show that (a) the overall encoding time could be reduced by 588 times, being the DMA transfer the bottleneck of our design; (b) Rate/Distortion performance has no significant variations when using different CTU and search area configurations; (c) the encoding delay will strongly depend on the size of both CTU and search area sizes.