Reference table based cache design using LRU replacement algorithm for Last Level Cache
Reishi Kumaar T., Anamika Shukla Sharma, Madasu Vijay Bhaskar · 2016
The advancements in the field of VLSI design allow multiple cores to be integrated on a single microprocessor chip. With the saturation in the scaling down of transistors to increase speed and performance, it is highly imperative to develop multi-core architectures for increased performance. But the increase in the core count per chip makes it more critical to design an efficient memory sub-system especially for the last level cache (LLC) that is shared among all the cores in a processor. The efficient utilization of the LLC is a dominant method to achieve the best microprocessor throughput. In this paper, the Reference Table (RT) based cache design for LLC of multi-core microprocessor is proposed using LRU replacement policy. The proposed RT Cache design adjusts itself based on the workload and automatically changes the utilization of the cache blocks to cope with the changes in the set access pattern so as to decrease the number of conflict misses. Also, at the same time it takes the advantage of accessing multiple cache blocks simultaneously so as to facilitate fast cache search of the set-associative LLC. The proposed architecture has been tested for a four core x86 multi-core architecture using Multi2sim open source tool. It is observed from the simulations that the proposed design provides an increase of 15.16% in cycles per second and 2.28% increase in hit ratio for L2 cache as compared to the n-way set associative cache.