Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor
Brian Zimmer, Pi-Feng Chiu, Borivoje Nikolić, Krste Asanović · 2016
The presented processor lowers SRAM-based cache Vminby using three architectural techniques-bit bypass (BB), dynamic column redundancy (DCR), and line disable (LD)-that use low-overhead reprogrammable redundancy (RR) to avoid failing bitcells and therefore increase the maximum bitcell failure rate in processor caches. In the 28nm chip, the Vminof the 1MB L2 cache is reduced by 25%, resulting in a 49% power reduction with a 2% area overhead and minimal timing overhead.