Simulated performance of a class of vector processors
Claudio Luis Amorim · Spiral (Imperial College London) · 1984
is that of i n s t r u c t i o n hazards in wh i c h instru ct io ns cann ot be is sued be c a u s e their r e q u ir ed re sources are not a v ai la bl e and prog ra m exe c u t i o n is delayed.Th i s s i tu at io n is m o r e critical in ve c t o r proces so rs w h e r e v e c t o r in s t r u c t i o n s taking mo r e time to e x ec ut e can pr o d u c e m o r e s e v e r e hazards.T h e e x e c u t i o n time d i f f er en ce among instru ct io ns in these pr o c e s s o r s has b e e n allevi at ed by ov er la pp in g i n s t r u c t i o n issue an d e x e c u t i o n so that they are issued se qu en ti al ly wi t h o u t having to w a i t for their pr ed ec e s s o rs to finish u n le ss a ha z a r d (dependency) oc cu rs w h e n the d e p e n d e n t i n s t ru ct io n ha lts the issue flow.Be ar in g this i n mind, this w o r k i n v e s t i g a t e s the p e r f o r m a n c e of a p a r a m e t e r i z e d v e c to r pr o c e s s o r m o d e l in w h i c h the i n s t r u c t i o n ha zards c a n be tackled by v a r y i n g the a r c h i t e c t u r a l mechanisms.T h e m o d e l s u pp or ts the CRAY1 a r c h i t e c t u r a l elem en ts such as the reg i s t e r file s t r u c t ur e( ve ctor, ad dress and scalar registers), b u ff er i n g of m a i n s t o r e ( d a t a and i n s t r u c t i o n buffers), m a i n store interleaving, func ti onal unit c o m p o s i t i o n and adds to it an in st r u c t i o n lo ok -a he ad cont ro l m e c h a n i s m an d an a u t o m a t i c da ta cache.A timi ng s i m u l a t o r w r i t t e n in P A S C A L of this p a ra me te ri ze d mo de l has b e e n de v e lo pe d and a s s i s t s the p e r f or ma nc e e v a l u a t i o n of d i ff er en t pro c e s s o r de signs by pr ov id in g accu ra te timing diag no st ic s of every in s t r u c t i o n ha z a r d source.A set of F O R T R A N p r o g ra ms run in the CRAY1 is us ed to v a l i d a t e the s i m u la to r and to e v a l u a t e the p e r f or ma nc e of the class of v e c t o r a r ch i t e c t ur es w h i c h the m o d e l encompasses.S i m u l a t i o n cost s w i l l be p r es en te d and the v a li di ty of a p pr oa c h to v e c t o r p r o c e s s o r p e r f o r m a n c e e v a l ua ti on w i l l and co n c l u s i o n s w i l l be presented.this ge neral be discus se d -iii -ACKNOWLEDGMENTS I a m i n de bt ed to m y su pe rv is or P r o f e s s o r D. J. Howarth, for his gui d a n c e and e n c o u r a g e m e n t throug ho ut the course of this work.I w o u l d like to t h an k Mr. Chris L a z o u of U n i v e r s i t y of L o n d o n C o m p u t e r C e n t r e for hi s s u pp ort in us i n g the CRAY1 C o m p u t e r fa ci li ti e s at D a r e sb ur y .T h i s thesis c o ul d not have b e en w r i t t e n w i t h o u t the joined financial s u p port of the B r a z i l i a n P o s G r a d u a t e C o o r d i n a t i o n P r og ra m( CA PE S) and U n i v e r s i d a d e F e d e r a l do R i o de Janeiro.I am de e p l y g r a t e f u l to my family and to my friends for their mora l su pport wi t h o u t w h i c h this project w o u l d not have b e e n completed.