Reconfigurable floating point arithmetic components for DSP applications
K Raghavendra Karthik, K L Diwakara Reddy, Chetan K Pawar, K Sunitha, H. V. Jayashree · 2016
This paper presents the reconfigurable floating point design of addition, subtraction, and Multiplication units which are used to design two blocks namely Fused Addition Subtraction (FAS) unit and Fused Dot Product (FDP) unit. The reconfigurable floating point addition and multiplication units are applied in the design of a Discrete Hilbert Transform Computation Unit and the FAS, FDP units are used in the design an 8-point complex Discrete Fourier Transform (DFT) unit and Inverse Discrete Fourier Transform (IDFT) unit based on the Radix-2 Decimation in Frequency (DIF) Fast Fourier Transform (FFT) algorithm. Discrete Hilbert Transform (DHT) is one of those Digital Signal Processing Transformations, which is applied on real valued sequences in order to obtain the analytical representation of the same. Reconfigurable architectures are designs, which can be employed for all the precision formats (Single Precision, Double Precision and Extended Precision etc.) given by the IEEE 754 standard by making minimal changes to register sizes. These components are implemented in Verilog on Virtex-6 FPGA. The synthesis results show that the reconfigurable systems designed are faster when used in DHT units and occupy significantly less area about 65% in terms of Slices compared to counterparts when used in DFT/IDFT units designed with FAS and FDP units.