A data extraction and debugging framework for large-scale MPSoCs
Marcelo Ruaro, Henrique Chamorra, Felipe Pfeifer Rubin, Alexandre M. Amory, Fernando Moraes · 2016
Although it is possible to design and manufacture MPSoCs with hundreds of processors, there is still a gap in the ability to debug hardware, software, and applications for such chips. Current state-of-the-art works related to MPSoC debugging suffer from poor integration, scalability in data storage, and simple graphical data representation. This work proposes a modular debugging framework to aid the software development for large-scale MPSoCs. The framework contains two parts: back-end and front-end. The back-end contains a generic model for extraction and storage of communication and computation data. The frontend comprises a graphical debugging toolset, which provides intuitive debugging tools for the communication and computation data events. A key point of the proposal is to be generic and applicable to different MPSoC architectures due to the decoupling of the back-end and the front-end components of the framework. A data extraction layer abstracts the MPSoC architecture by defining a standard structure to database insertion. The framework is validated in an MPSoC platform described in SystemC RTL (clock-cycle accurate), addressing MPSoC sizes of up to 400 processors.