Low-power and area efficient N-bit parallel processors on a chip
Vijaya Sree Boddu, B. Naresh Kumar Reddy, M. Kranthi Kumar · 2016
Multiprocessor system-on-chip (MPSoC) architectures have risen as a prevalent answer to the ever-increasing performance reduce the power consumption requirements, that are customized to a specific application have the potential to achieve efficient area, while additionally obliging low power consumption. The power consumed and area of the system majorly depends on the memory Communication medium of Processors, some issues involved in Memory communication of processors. In this Paper we avoid that issue and show two separate techniques to reduce the power consumption and area. The main technique is Scratch Pad Memory (SPM) replacement instead of cache replacement, second technique is Network on Chip (NOC) instead of Advanced Microcontroller Bus Architecture (AMBA) communication medium between processors.