Design of reversible full subtractor using new reversible EVNL gate for low power applications
E. V.Naga Lakshmi, Nuka Siva Sankara Reddy · 2016
Recent years Reversible Logic Gates are proved to be more efficient in terms of Power dissipatio Hence for low power applications RLG circuits are developed by most of the researchers. All Reversible Logic Gates were compared with quantum cost, Garbage outputs and Garbage inputs, but power measurement for all these gates have not been done though it was the most important parameter for low power applications. This paper presents power analysis of proposed reversible full subtractor. Measurement of power for the proposed reversible gate based 1 bit full subtractor and conventional irreversible 1 bit full subtractor has been done by using Microwind tool and observed that reversible circuits consume less power when compared to conventional one. Then 2bit, 4 bit, 8 bit and 16 bit subtractors were designed. Compared to the conventional 8 bit parallel subtractor reversible 8 bit full subtractor dissipates 73.99% less power.