When Clustering Shows Optimality towards Analyzing Stuck-at Faults in Channels of On-chip Networks
Biswajit R. Bhowmik, Jatindra Kumar Deka, Santosh Biswas · 2016
With the ever shrinking dimension of a chip on a die, it is evident that the channels of on-chip networks (NoCs) are often exposed to logic level manufacturing faults such as stuck-at faults. The faults coercively put the networks into miscellaneous system level failures like packet corruption, misrouting, and dropping. Thus, the reliability has become a special interest. Additionally, the performance of the NoCs is somewhat deviated. This paper proposes a distributed and time-efficient on-line test model that addresses stuck-at faults in interswitch and local channels of NoCs as well as analyze the effect of the faults on various performance metrics. Fault simulations achieve 100% coverage metrics and show that the proposed test model takes same test clocks to detect the faults in larger NoCs. Further, online evaluation of the proposed test model reveals that it speeds more than 16 times up on a set of NoCs. Simultaneously, we observe packet latency is improved to 20.17-44.45% while energy consumption by a packet flit is reduced to 16.96-39.40% on these NoCs. The improvements may grow with NoC size.