Algorithms and vlsi architectures for low-density parity-check codes: part 2 - efficient coding architectures
Kiran Gunnam, Joan Marc Català Pérez, Francisco García-Herrero · IEEE Solid-State Circuits Magazine · 2017
This article is the second of a two-part tutorial about low-density parity-check (LDPC) codes. (The first part appeared in the Fall 2016 issue.) Here, we describe the min-sum decoding algorithm and explain the very-largescale integration (VLSI) architectures for nonlayered and layered decoders and the techniques to reduce memory and logic requirements in their implementations, pointing out the advantages and disadvantages of each.