A fault tolerant router with optimized an colony algorithm
N. Mohanapriya, C. Priya · 2016
Network on Chip (NOC) approach has appeared as a solution for on-chip communications to allow integrating various processors and on-chip memories into a single chip. During the field operation of NOC, the latent hard faults technologically advanced in First In First Out buffers (FIFO). By using on line test techniques, that faults have been spotted. In this technique, the test has to be repeated occasionally to avoid the gathering of faults. Also design router architecture with shared queues (RoShaQ) among input ports which exploits the buffer operation by permitting the sharing multiple buffer queues. The efficient use of shared buffers achieves highest possible throughput when the network load becomes heavy. when the lighter traffic load can achieves low latency by allowing packets to effectively bypass these shared queues. For load balancing in faulty networks the ant colony optimization-based fault-aware routing (ACO-FAR) algorithm is propose. The best probabilistic technique is an ant colony optimization algorithm (ACO) for solving computational problems. This technique can be reduced to result a good and shortest paths through graphs. For responding an obstacle implements the three mechanisms as: 1) fault notification; 2) search the path; and 3) select the path.