Correcting Two Deletions and Insertions in Racetrack Memory
Alireza Vahid, Georgios Mappouras, Daniel J. Sorin, A.R. Calderbank · arXiv (Cornell University) · 2017
Racetrack memory is a non-volatile memory engineered to provide both high density and low latency, that is subject to synchronization or shift errors. This paper describes a fast coding solution, in which delimiter bits assist in identifying the type of shift error, and easily implementable graph-based codes are used to correct the error, once identified. A code that is able to detect and correct double shift errors is described in detail.