Computer aided design of cluster-based ASIPs
Hangcheng Yang · TU/e Research Portal · 2013
Portable consumer electronic devices, such as smart phones or tablets, play a very important role in today’s world. To well serve the portability, these kinds of devices have to satisfy rigorous requirements of small size and high energy efficiency under limited energy resources, and have to deliver a high performance at the same time. Application-specific Instruction-set Processors (ASIPs are commonly used in portable devices to allow satisfaction of these stringent requirements related to size, energy efficiency and performance. ASIP design is however a complex iterative procedure that currently only partly automated. This results in a high development effort. Due to the complex and non-automated ASIP Design Space Exploration (DSE), the ASIP design time substantially affects the time-to-market. The research reported in this Master thesis is related to the development of an efficient Electronic Design Automation (EDA) method for the synthesis of ASIPs to achieve a substantial development time reduction without decreasing the design quality. It targets the Intel (Silicon Hive) VLIW ASIPs. The main aim of this Master project is to propose a systematic method of cluster-based ASIP design enabling substantial interconnection reduction and energy savings, to implement the method as an EDA tool, and to perform related design experiments. With the assistance of this tool, we have conducted experimental research on cluster-based ASIP architecture. The results showed that the cluster-based ASIP architecture achieved 15-20% energy reduction compared to the non-clustered one, while maintaining almost the same performance. In certain cases, the cluster-based ASIPs provide even better performance, due to the fact that their clustered architecture helps the compiler to achieve better scheduling results.