Cost effective FPGA implementation for hard decision LDPC decoders
Alexandru Amaricăi, Oana Boncalo · 2016
This paper proposes a QC-LDPC partial parallel architecture that implements a hard decision message passing algorithm based on Gallager-B decoding. The proposed architecture uses an optimized variable node unit, with adaptive threshold, suitable for irregular LDPC codes. We present implementation results for WiMAX rate 1/2 code for FPGA technology. These indicate a cost reduction of 2.5x in logic, and 25% in memory with respect to Min-Sum algorithm with 2 bits.