The 5th Generation 28nm 8-Core VLIW Elbrus-8C Processor Architecture
Aleksey S. Kozhin, Nikita Yu. Polyakov, Daniil M. Alfonso, Roman V. Demenko, Pavel A. Klishin, Evgeniy S. Kozhin, Слесарев Михаил Владимирович, Elena V. Smirnova, Dmitriy A. Smirnov, Pavel A. Smolyanov, Vitaliy O. Kostenko, Feodor A. Gruzdov, Vladimir V. Tikhorskiy, Yuli Kh. Sakhin · 2016
Elbrus is an explicitly parallel VLIW instruction set architecture developed by MCST. In this paper, we introduce the microarchitecture of the 5th generation 8-core Elbrus-8C processor implemented on 28nm. Elbrus-8C has 5x the peak performance for floating-point operations as compared with its predecessor, the Elbrus-4C processor, due to improved single-core performance and doubled number of cores. Microarchitecture enhancements include a 16 MB shared third-level cache, high-bandwidth, low-latency on-chip network, and a new cache coherence protocol. Elbrus-8C improves bandwidths of memory and I/O subsystems using four DDR3-1600 memory channels and a new 8 GBps full-duplex I/O link. The Elbrus-8C processor also offers energy saving, reliability, and die yield improvement mechanisms required due to large die area and power.