Mixed-criticality transactional memory controller for embedded systems
Zaher Owda, Roman Obermaisser · 2016
The pervasiveness of multi-core platforms and the trend towards mixed-criticality applications are major technology drivers in the area of embedded systems. Although transactional memories offer the potential to radically simplify the development of these systems, fault isolation and temporal predictability are open research challenges. This paper introduces a priority-based hardware transactional memory controller for mixed-criticality systems, which offers algorithms for predictable and selective conflict resolution. The memory controller is part of a multi-core architecture with a mapping to a deterministic time-triggered interconnect. As a consequence, fault propagation to higher criticality is prevented and the timing analysis of safety-relevant transactions can abstract from lower criticality levels. The presentation of the architecture and the explanation of the algorithms is complemented by the formal analysis of the WCET. In addition, an automotive use case with a simulation environment serves for the evaluation of the temporal behavior of the architecture and the memory controller.